The rapid growth of LED (light-emitting diode) lighting has led to a wide variety of integrated circuit devices to provide controlled power to LEDs. In many applications, real-time changes in LED output intensity are required. This function is commonly referred to as dimming control. One method of effecting dimming control of an LED is pulse-width modulation. Pulse-width modulation involves the commutating, or starting, stopping, and restarting, of a substantially constant LED current for short periods of time. In order to avoid a flickering effect, this start-restart cycle is performed at a frequency of about 200 Hz or faster, which makes the starting and restarting of the LED current undetectable to the human eye. The apparent brightness of the LED is determined by the time-averaged current through the LED. Thus the dimming of the LED is proportional to the duty cycle of the dimming waveform.
FIG. 1 is a circuit diagram of an LED power switching circuit that enables dimming via pulse-width modulation. Current source 110 supplies current to LED 120, as well as to MOSFET switch 130. Turning the power switch 130 off and on, by making the voltage VG applied to the gate go low or high, controls the current to the LED 120. When the switch 130 is off, the current Iinput flows through the LED 120. When the switch 130 is on, the current Iinput flows through the switch 130, shunting the current away from the LED 120. Thus the dimming of the LED is controlled by the duty cycle of the gate control signal VG.
It is desirable that this turning on and off of the power switch 130 be soft in order reduce electromagnetic emissions. Hard edges in the gate control signal VG and in the current ILED through the LED 120 cause unwanted frequency harmonics. Various applications have different electromagnetic interference standards that must be complied with, so it is desirable to regulate the rate of change of the gate control signal voltage VG and the rate of change of the LED current.
Conventionally, a slew rate controlled gate driver circuit is used to drive the power switch 130 in order to achieve soft turn on and soft turn off. FIG. 2 is a circuit diagram of a conventional slew rate controlled gate driver circuit 200. The slew rate controlled gate driver circuit 200 includes a PMOS transistor S3 210 and an NMOS transistor S4 220. The gates of S3 210 and S4 220 are coupled together to receive a control pulse VCTRL. The drains of S3 210 and S4 220 are coupled together to provide a gate control signal VG. This gate control signal VG can be provided to the gate of switch 130 of FIG. 1 to control the switch turn on/off. Slew rate control is provided by the current sources I1 230 and I2 240. Current source I1 230 controls the rise rate of gate control signal VG, and current source I2 240 controls the fall rate of VG. The rise rate of VG is dependent upon the capacitance of the gate of switch S3 210 and the value of current I1. Similarly, the fall rate of VG is dependent upon the capacitance of the gate of switch S4 220 and the value of current I2. Thus I1 and I2 are selected to provide the desired rise and fall rates of gate control signal VG. This can also be implemented using resistors in place of I1 and I2 or using a resistor in series with the gate control signal VG. While the gate driver circuit 200 regulates the slew rate of the gate control signal VG, thus achieving soft turn on/off of the switch 130, it causes a stretching of the current pulse in the LED 120, resulting in a difference between the input pulse and the actual duration for which the LED 130 is on, as will be described below with respect to FIG. 3.
FIG. 3 is a timing chart showing the relationship between the input control pulse VCTRL provided to the gate driver circuit 200, the gate control signal VG, and the current ILED through the LED 120. Following the fall 310 of the VCTRL input, the gate voltage VG rises slowly, at a controlled slew rate. The rate of the rise of VG is controlled by current source I1 230. As the gate control signal VG rises above the on/off threshold VTH of the power switch 130 at point 320, the switch 130 starts conducting and the current ILED in the LED 120 begins dropping as more of the current Iinput flows into the switch 130. When ILED drops to zero (at point 330) and the switch current peaks, the drain-to-source voltage VDS across the switch 130 starts dropping. During the time that VDS is discharging, the gate control signal VG stays flat. This is known as the Miller plateau and is shown in FIG. 3 at 340. At point 350, VG starts rising again once VDS has dropped to its minimum value, turning the switch 130 fully on. During turn-off of the switch 130, the operation is reversed, and current source I2 240 controls the rate of fall of gate control signal VG.
Thus it can be seen that the conventional slew rate controlled gate driver circuit, such as gate driver circuit 200, causes a stretching of the current pulse in the LED, resulting in a substantial difference between the input pulse VCTRL and the actual duration for which the LED is on. Because very small duration pulses cannot be achieved, there is loss of dimming resolution.